Field of the Invention
The invention relates a loop bandwidth adjusting method for a phase-locked loop (PLL) unit in a phase recovery module and associated loop bandwidth adjusting unit and phase recovery module, and more particularly to a loop bandwidth adjusting method that optimizes a bandwidth of a PLL unit through calculating phase errors in a phase recovery module, and associated loop bandwidth adjusting unit and phase recovery module.
Description of the Related Art
A phase-locked loop (PLL) circuit is used to generate a periodic output signal, which is expected to have a constant phase relationship with a periodic input signal. PLL circuits are extensively applied in various types of circuit systems, for example but not limited to, clock and data recovery circuits, transceivers and frequency synthesizers, in wireless communication systems.
Based characteristics (e.g., the frequency) of an input signal and circuit requirements, a loop bandwidth and a damping factor of the PLL circuit need to be appropriately designed in order to achieve balance between a locking speed and locking accuracy. However, because characteristics of an input signal changes with time due to environment factors (e.g., noises), the performance of the PLL circuit may not persistently maintain a designed optimum value if the loop bandwidth and damping factor of the PLL circuit stay constant. Therefore, there is a need for a solution that adaptively adjusts characteristics of the PLL circuit during operation.